bus interface controller

基本解释

The PCI top-level block design is first presented in terms of the bus interface controller.
在分析PCI总线接口控制器基本功能的基础上，给出其顶层设计。
The FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing.
根据PCI总线操作时序，提出了从设备接口控制器的有限状态机模型。
PCI bus is high bandwidth, being independent of CPU, high capacity bus. The bus interface controller design is its key techniques to application .
PCI总线是一种高带宽、独立于CPU的高性能总线，总线接口控制器的设计是其应用的关键所在。